1. Field of the Invention
The present invention relates to a digital phase comparing apparatus, and more specifically to a digital phase comparing apparatus for use in, for example, a digital frequency synthesizer having a phase locked loop employed in a citizen band transceiver, a television receiver, a radio receiver and the like.
2. Description of the Prior Art
Recently radio receivers employing a so-called digital frequency synthesizer using a phase locked loop as a local oscillator have been proposed and put in practical use. FIG. 1 shows a block diagram of such a radio receiver employing a digital frequency synthesizer as a local oscillator. Referring to FIG. 1, a tuning and detecting circuit 2 is connected to receive a high frequency signal received by an antenna 1 and to provide an audio signal output. The tuning and detecting circuit 2 is structured to comprise a voltage controlled oscillator 3 as a local oscillator. The output signal from the tuning and detecting circuit 2 is applied to an audio amplifier 4, where the signal is amplified. The output of the audio amplifier 4 is applied to a speaker 5. As well known, in a digital frequency synthesizer radio receiver, a local oscillator is implemented by a voltage controlled oscillator, which is connected to constitute a phase locked loop such that the oscillation frequency is controlled by the phase locked loop.
The phase locked loop shown in FIG. 1 comprises a phase comparator 7 structured to compare the phase of the output of a frequency divider 8 the frequency of which is f1 and the phase of the output of a programmable frequency divider 6 the frequency of which is f2. The frequency divider 8 is structured to frequency divide at a frequency division ratio 1/n the output of a reference oscillator 9 to provide a frequency signal of the frequency f1. The programmable frequency divider 6 is structured to frequency divide at a variable frequency division ratio 1/N the output of the above described voltage controlled oscillator 3 included in the tuning and detecting circuit 2 to provide a frequency signal of the frequency f2. The phase comparator serves to provide a voltage signal proportional to the phase difference between the above described two frequency signals f1 and f2 to a charge pump 10. The output of the charge pump 10 is fed back through a low-pass filter 11 to the above described voltage controlled oscillator 3 as a control voltage. The programmable frequency divider is provided such that the local oscillation frequency, i.e. the oscillation frequency of the voltage controlled oscillator 3 is variable in association with a channel selected by a channel selector 13. More specifically, the data concerning the broadcasting frequencies of various broadcasting stations is in advance stored in a memory 12 and the data corresponding to the broadcasting frequency of a desired broadcasting station is selectively read from the memory 12 responsive to selection of a desired channel by means of the channel selector 13. The data read from the memory 12 is set in the programmable frequency divider 6 as a frequency division ratio. The channel thus selected by the channel selector 13 may be displayed by means of a display 14, as necessary.
The present invention relates to a phase comparator for use in such a digital frequency synthesizer. Various circuit configurations have been heretofore proposed as such a phase comparator. A prior art phase comparator of interest to the present invention is seen, for example, in U.S. Pat. No. 3,610,954, issued Oct. 5, 1971 to Ronald L. Treadway, entitled "PHASE COMPARATOR USING LOGIC GATES" and U.S. Pat. No. 3,714,463, issued Jan. 30, 1973 to Jon M. Laune, entitled "DIGITAL FREQUENCY AND/OR PHASE DETECTOR CHARGE PUMP". A counterpart British patent corresponding to the above described U.S. Pat. No. 3,610,954 has been granted as British Pat. No. 1,328,031.
FIG. 2 shows a schematic diagram of a prior art phase comparator disclosed in the above referenced U.S. Pat. No. 3,610,954. As seen from FIG. 2, the above referenced U.S. Pat. No. 3,610,954 comprises a circuit configuration, wherein for the purpose of signal detection one signal is applied to a NAND gate 74 through a NAND gate 71 while the other signal is applied to a NAND gate 74 through NAND gates 71' and 75. Thus, according to the prior art phase comparator as shown in FIG. 2, a disadvantage is encountered that a connection path for signal detection becomes long and hence stray capacitance becomes large. Furthermore, since the prior art phase comparator shown employs multiple input gates such as the NAND gates 74, 74' and 75, the input capacitance becomes accordingly large. Because of the above described large stray capacitance and input capacitance, a signal is so much delayed that a small phase difference can be hardly detected. Accordingly a so-called spike phenomenon is liable to occur wherein a p-channel MOS transistor 104 and an n-channel MOS transistor 105 of the charge pump 10 becomes simultaneously conductive. On the other hand, as shown in FIG. 2, the charge pump 10 are typically implemented by CMOS field-effect transistors; however, employment of CMOS field-effect transistors in the charge pump 10 necessitates employment of an inverter 106 between the NAND gate 74' and the gate of the n-channel MOS transistor. The reason is that a circuit configuration concerning the NAND gate 74 and the circuit configuration concerning the NAND gate 74' are structured in a symmetrical manner. Furthermore, if and when the charge pump 10 is implemented by CMOS field-effect transistors, as shown in FIG. 2, then a small signal corresponding to a small frequency difference does not exceed an input threshold voltage of the inverter 106, inasmuch as such input threshold voltage is approximately 1/2 V.sub.DD. Accordingly, the charge pump 10 becomes irresponsive to an input signal, which makes it impossible to detect a small phase difference. Thus, according to a conventional phase comparator as shown in FIG. 2, the sensitivity of phase detection becomes low and it follows that a carrier to noise ratio of the phase locked loop and thus a signal to noise ratio of a radio receiver is degraded. Furthermore, assuming that such a conventional phase comparator as shown in FIG. 2 is implemented by way of large scale integration, the circuit pattern becomes complicated, inasmuch as the prior art shown is of a random gate type. The problem of complicated circuit pattern is aggravated by an increased number of devices in the circuit.
FIG. 3 shows a schematic diagram of the prior art phase comparator disclosed in the above referenced U.S. Pat. No. 3,714,463. The phase comparator shown in FIG. 3 comprises two flip-flops 76 and 76' and three NOR gates 77, 78 and 78'. Since the FIG. 3 phase comparator is structured such that coincidence or non-coincidence of the outputs of two J-K flip-flops 76 and 76' is detected and is fed back, a coincidence gate, i.e. the NOR gate 77, is necessarily required. The prior art phase comparator shown in FIG. 3 still requires a larger number of devices, which makes the signal detection path long and accordingly is liable to cause a loss of the signal.